In order to synchronize a multi-node, multi-processor system, each processor clock in the system must be relatively synchronized with the other processor clocks. To accomplish this, the approximate time must be known at certain processing points, and the time needs to be approximately the same throughout the system.
In the system, each node has a clock counter and each processor on that node reads that clock counter. Unfortunately, each counter clock, and hence each node, in the system runs at a slightly different clock frequency. The difference in clock frequencies is because the crystals in each counter are not exactly identical. The different crystal frequencies allow the counters to drift apart in their time values. The physical differences in the crystals cannot be controlled.
The known prior art solves this drifting problem by using extra wires connected between each node. These wires provide separate signal paths for conveying synchronizing signals. After a time interval, which is defined by the hardware, a synchronization packet is distributed via the wire, and each node then receives that signal and changes its counter time appropriately.
The problem with the prior art solution is that it is expensive in terms of the costs to performance because of the extra signal paths. The prior art solution also added complexity to the system because the wires require additional connections which can introduce more problems and errors in the circuit, particularly with respect to grounding between the connections.
Therefore, there is a need in the art for a system and method for providing access to low skew clocks on different nodes that are synchronized with each other.
There is also a need in the art for a system and method to synchronize the clocks on the different nodes without introducing latencies during synchronization.
There is also a need in the art for a system and method to synchronize the clocks on the different nodes without reducing system performance.